Power estimation and power optimization policies for processor-based systems

This PhD Thesis proposes new and effective approaches to reduce and estímate the power consumption in processor-based architectures. This work targets embedded systems, inorder and out-of-order processors, cache hierarchies and MPSoCs. Our approaches are designad to reduce or estimate the power consumption while keeping the performance constraints of the application and allowing the porting to other processor architectures without a hard effort by the designen In this context, a first work was the design of a cache power estimation tool (called IN^ CAPE), which works in parallel with the processor simulator. The power estimation utihty bases its results on an analytical power model, which has been fed with the expHcit calculation of the statistical switching activity. After that, reducing the power consumption in the register file of the processor architecture was the goal of the research. Given that the register file is one of the most power-hungry devices, firstly an efficient hardware mechanism to tum the unused registers of the register file into a low power state has been described. A DVS technique is used to keep the Information stored in the registers while reducing the power consumption to a mínimum. This hardware technique has been compared to an approach based on a power-aware compiler, which modifies the register assignment to improve the results obtained with the banking of the register file, as well as to reduce the number of required ports. Out-of-order architectures have also been addressed, with a higher degree of complexity. For these systems, compiler and hardware approaches have also been proposed to efficiently reduce the power consumption of the register file. Finally, MPSoCs are also the new paradigm of high-performance microprocessor design, where the power dissipation becomes an even more dramatic problem. These architectures present complex design issues where the power-performance trade-off has to be carefully analyzed in order to bring efficient designs. The work presented in this Ph. D. aims at overcoming the limitation of theoretical and highly abstract models, unable to target the This PhD Thesis proposes new and effective approaches to reduce and estímate the power consumption in processor-based architectures. This work targets embedded systems, inorder and out-of-order processors, cache hierarchies and MPSoCs. Our approaches are designad to reduce or estimate the power consumption while keeping the performance constraints of the application and allowing the porting to other processor architectures without a hard effort by the designen In this context, a first work was the design of a cache power estimation tool (called IN^ CAPE), which works in parallel with the processor simulator. The power estimation utihty bases its results on an analytical power model, which has been fed with the expHcit calculation of the statistical switching activity. After that, reducing the power consumption in the register file of the processor architecture was the goal of the research. Given that the register file is one of the most power-hungry devices, firstly an efficient hardware mechanism to tum the unused registers of the register file into a low power state has been described. A DVS technique is used to keep the Information stored in the registers while reducing the power consumption to a mínimum. This hardware technique has been compared to an approach based on a power-aware compiler, which modifies the register assignment to improve the results obtained with the banking of the register file, as well as to reduce the number of required ports. Out-of-order architectures have also been addressed, with a higher degree of complexity. For these systems, compiler and hardware approaches have also been proposed to efficiently reduce the power consumption of the register file. Finally, MPSoCs are also the new paradigm of high-performance microprocessor design, where the power dissipation becomes an even more dramatic problem. These architectures present complex design issues where the power-performance trade-off has to be carefully analyzed in order to bring efficient designs. The work presented in this Ph. D. aims at overcoming the limitation of theoretical and highly abstract models, unable to target the desired functional simulation and power estimation. This work also presents interesting results in terms of dynamic power management, voltage/frequency scaling and design space exploration in MPSoCs

Proactive and reactive thermal aware optimization techniques to minimize the environmental impact of data centers

Data centers are easily found in every sector of the worldwide economy. They are composed of thousands of servers, serving millions of users globally and 24-7. In the last years, e-Science applications such e-Health or Smart Cities have experienced a significant development. The need to deal efficiently with the computational needs of next-generation applications together with the increasing demand for higher resources in traditional applications has facilitated the rapid proliferation and growing of Data Centers. A drawback to this capacity growth has been the rapid increase of the energy consumption of these facilities. In 2010, data center electricity represented 1.3% of all the electricity use in the world. In year 2012 alone, global data center power demand grep 63% to 38GW. A further rise of 17% to 43GW was estimated in 2013. Moreover, Data Centers are responsible for more than 2% of total carbon dioxide emissions

Leveraging heterogeneity for energy minimization in data centers

Energy consumption in data centers is nowadays a critical objective because of its dramatic environmental and economic impact. Over the last years, several approaches have been proposed to tackle the energy/cost optimization problem, but most of them have failed on providing an analytical model to target both the static and dynamic optimization domains for complex heterogeneous data centers. This paper proposes and solves an optimization problem for the energy-driven configuration of a heterogeneous data center. It also advances in the proposition of a new mechanism for task allocation and distribution of workload. The combination of both approaches outperforms previous published results in the field of energy minimization in heterogeneous data centers and scopes a promising area of research

Hacia la conciencia social del consumo energético en centros de datos

Ante el problema creciente del consumo en los centros de datos, unido a la adopción paulatina de las mejores prácticas actuales para mejorar la eficiencia energética, se hace imprescindible un cambio radical en el enfoque de la energía en dichos centros de datos para poder seguir reduciendo de manera significativa su impacto medioambiental. En este artículo presentamos una propuesta inicial para la optimización integral del consumo de energía en centros de datos, que ha sido validado en un escenario de monitorización poblacional de salud, con ahorros de hasta un 50% frente al estado del arte en eficiencia energética. Defendemos una conciencia global del Estado y el comportamiento térmico del centro de datos, utilizando modelos predictivos para anticipar las variables determinantes para la optimización. Además, las estrategias de optimización energética de los centros de datos del futuro tienen que ser sociales: los distintos elementos (servidores, software de gestión, sistemas de refrigeración) deben tener cierta conciencia del estado de los demás elementos del sistema y de cómo el entorno los puede perjudicar o favorecer, buscando el consenso en estrategias colaborativas para reducir el consumo total

Runtime data center temperature prediction using Grammatical Evolution techniques

Depto. de Arquitectura de Computadores y AutomáticaFac. de InformáticaTRUEMinisterio de Economía y Competitividad (MINECO)pu

A hardware mechanism to reduce the energy consumption of the register file of in-order architectures

This paper introduces an efficient hardware approach to reduce the register file energy consumption by turning unused registers into a low power state. Bypassing the register fields of the fetch instruction to the decode stage allows the identification of registers required by the current instruction (instruction predecode) and allows the control logic to turn them back on. They are put into the low-power state after the instruction use. This technique achieves an 85% energy reduction with no performance penalty

Thermal modeling and analysis of 3D multi-processor chips

As 3D chip multi-processors (3D-CMPs) become the main trend in processor development, various thermal management strategies have been recently proposed to optimize system performance while controlling the temperature of the system to stay below a threshold. These thermal-aware policies require the envision of high-level models that capture the complex thermal behavior of (nano)structures that build the 3D stack. Moreover, the floorplanning of the chip strongly determines the thermal profile of the system and a quick exploration of the design space is required to minimize the damage of the thermal effects

A novel energy-driven computing paradigm for e-health scenarios

A first-rate e-Health system saves lives, provides better patient care, allows complex but useful epidemiologic analysis and saves money. However, there may also be concerns about the costs and complexities associated with e-health implementation, and the need to solve issues about the energy footprint of the high-demanding computing facilities. This paper proposes a novel and evolved computing paradigm that: (i) provides the required computing and sensing resources; (ii) allows the population-wide diffusion; (iii) exploits the storage, communication and computing services provided by the Cloud; (iv) tackles the energy-optimization issue as a first-class requirement, taking it into account during the whole development cycle. The novel computing concept and the multi-layer top-down energy-optimization methodology obtain promising results in a realistic scenario for cardiovascular tracking and analysis, making the Home Assisted Living a reality

II Jornada Aprendizaje Eficaz con TIC en la UCM

Las Tecnologías de la Información y las Comunicaciones siguen en el núcleo de la innovación docente, estimulando nuevas visiones del proceso educativo y potenciando nuestras aulas. La pandemia nos ha obligado a hacer de una crisis una oportunidad, cambiando para siempre el proceso educativo. Aunque ya no hacemos clases híbridas de forma regular, hemos incorporado estas nuevas herramientas a nuestra práctica diaria. Las líneas temáticas seleccionadas este año fueron: experiencias educativas eficaces en el Campus virtual, las TIC en el aula, materiales digitales, nuevas tendencias educativas, las TIC aplicadas a metodologías didácticas activas e incorporación de los ODS mediante TIC a la educación universitaria. El programa incluía también la presentación de una selección de cinco proyectos de innovación y mejora de la calidad docente por parte del vicerrectorado de Calidad. Para completar el programa, se invitaron dos ponencias. La primera, presentada por David Pacios Izquierdo, explicaba cómo pueden hacerse clases más inclusivas usando herramientas de código abierto que están disponibles en la web de la oficina del software libre. La segunda, presentada por Juan Antonio León Luis, mostraba un caso de éxito del uso de realidad virtual para entrenar a los obstetras en los tipos y maniobras de parto y que se usa en el hospital Gregorio Marañón

Leakage and temperature aware server control for improving energy efficiency in data centers

Reducing the energy consumption for computation and cooling in servers is a major challenge considering the data center energy costs today. To ensure energy-efficient operation of servers in data centers, the relationship among computa- tional power, temperature, leakage, and cooling power needs to be analyzed. By means of an innovative setup that enables monitoring and controlling the computing and cooling power consumption separately on a commercial enterprise server, this paper studies temperature-leakage-energy tradeoffs, obtaining an empirical model for the leakage component. Using this model, we design a controller that continuously seeks and settles at the optimal fan speed to minimize the energy consumption for a given workload. We run a customized dynamic load-synthesis tool to stress the system. Our proposed cooling controller achieves up to 9% energy savings and 30W reduction in peak power in comparison to the default cooling control scheme